U.S. Pat. No. 5,008,727 (“Standard cell having test pad for probing and semiconductor integrated circuit device containing the standard cells”) to Katsura et al., incorporated by reference herein, discloses placement of a testing pad in a standard cell.
U.S. Pat. No. 6,091,249 A (“Method and apparatus for detecting defects in wafers”) to Graham et al., incorporated by reference herein, discloses structures and methods for testing certain defects using a non-contact (“NC”) technique.
U.S. Pat. No. 6,452,412 B1 (“Drop-in test structure and methodology for characterizing an integrated circuit process flow and topography”) to Jarvis et al., incorporated by reference herein, discloses structures and methods for testing certain defects using an NC technique.
U.S. Pat. No. 6,949,765 B2 (“Padless structure design for easy identification of bridging defects in lines by passive voltage contrast”) to Song et al., incorporated by reference herein, discloses structures and methods for testing certain defects using an NC technique.
U.S. Pat. No. 7,101,722 B1 (“In-line voltage contrast determination of tunnel oxide weakness in integrated circuit technology development”) to Wang et al., incorporated by reference herein, discloses structures and methods for testing certain defects using an NC technique.
U.S. Pat. No. 7,105,436 B2 (“Method for in-line monitoring of via/contact holes etch process based on test structures in semiconductor wafer manufacturing”) to Zhao et al., incorporated by reference herein, discloses structures and methods for testing certain defects using an NC technique.
U.S. Pat. No. 7,518,190 B2 (“Grounding front-end-of-line structures on a SOI substrate”) to Cote et al., incorporated by reference herein, discloses structures and methods for testing certain defects using an NC technique.
U.S. Pat. No. 7,930,660 B2 (“Measurement structure in a standard cell for controlling process parameters during manufacturing of an integrated circuit”), to Ruderer et al., incorporated by reference herein, describes the use of test structures in fill cells for manufacturing optimization.
U.S. Pat. No. 7,939,348 B2 (“E-beam inspection structure for leakage analysis”), to Seng et al., incorporated by reference herein, discloses structures and methods for testing certain defects using an NC technique.
U.S. Pat. No. 8,039,837 B2 (“In-line voltage contrast detection of PFET silicide encroachment”) to Patterson et al., incorporated by reference herein, discloses structures and methods for testing certain defects using an NC technique.
U.S. Pat. No. 8,339,449 B2 (“Defect monitoring in semiconductor device fabrication”), to Fong et al., incorporated by reference herein, discloses structures and methods for testing certain defects using an NC technique.
U.S. Pat. No. 8,399,266 B2 (“Test structure for detection of gap in conductive layer of multilayer gate stack”) to Mo et al., incorporated by reference herein, discloses structures and methods for testing certain defects using an NC technique.
U.S. Pat. No. 8,421,009 B2 (“Test structure for charged particle beam inspection and method for defect determination using the same”) to Xiao, incorporated by reference herein, discloses structures and methods for testing certain defects using an NC technique.
U.S. Pat. No. 8,575,955 B1 (“Apparatus and method for electrical detection and localization of shorts in metal interconnect lines”) to Brozek, incorporated by reference herein, discloses structures and methods for testing certain defects using an NC technique.
U.S. Patent Publication 20090102501 A1 (“Test structures for e-beam testing of systematic and random defects in integrated circuits”) to Guldi et al., incorporated by reference herein, discloses structures and methods for testing certain defects using an NC technique.